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revision history 512mb AS4C32M16MD1A - 60 ball fbga package revision details date rev 1.0 preliminary datasheet dec 2015 alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 alliance memory inc. reserves the right to change products or specification without notice rev 1. 1 removed industrial temperature may 2016 rev 1. 2 adjust the temperature information july 2016 AS4C32M16MD1A-5bcn confidential - 1/56 - rev.1.2 july 2016
1. general description this AS4C32M16MD1A-5bcn is 536,870,912 bits synchronous double data rate dynamic ram. each 134,217,728 bits bank is organized as 8,192 rows by 1024 columns by 16 bits fabricated with alliance memory?s high perfo rmance cmos technology. this device uses a double data rate architecture to achieve hi gh- speed operation. the dou ble data rate architectur e is essentially a 2n- prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o balls. range of operating frequencies, programmable burst lengths and programmable latencies allow th e same device to be useful for a variety of high bandwidth and high performance memory system applications. 2. features ? vdd/vddq = 1.7~1.95v ? data width: x16 ? clock rate: 200mhz ? partial array self-refresh(pasr) ? auto temperature compensated self-refresh(atcsr) ? power down mode ? deep power down mode (dpd mode) ? programmable output buffer driver strength ? four internal banks for c oncurrent operation ? data mask (dm) for write data ? clock stop capability during idle periods ? auto pre-charge op tion for each burst access ? double data rate for data output ? differential clock inputs (ck and ck ) ? bidirectional, data strobe (dqs) ? pkg type x16 : 8.0 x 9.0mm 60 ball fpbga (fine pitch ball grid array) ? cas latency: 2 and 3 ? burst length: 2, 4, 8 and 16 ? burst type: sequential or interleave ? 64 ms refresh period ? interface: lvcmos ? table 1. speed gr ade information speed grade clock frequency cas latency t rcd (ns) t rp (ns) table 2. ordering information product part no org temperature max clock (mhz) AS4C32M16MD1A-5bcn 32mx 16 extended -30c to +85c package 60-ball fpbga 200 200 mhz 3 15 15 ddr 1-400 operating temperature range extended (-30c to +85c) AS4C32M16MD1A-5bcn confidential - 2/56 - rev.1.2 july 2016
3. pin description fpbga assignment figure 1 ? pi n description AS4C32M16MD1A-5bcn confidential - 3/56 - rev.1.2 july 2016
3.1 signal descriptions signal name type description ck,/ck input clock: ck and ck are differential clock inputs. all address and control input signals are sampled on the cr ossing of the positive edge of ck and negative edge of ck. input and output data is referenced to the crossing of ck and ck (both direct ions of crossing). internal clock signals are derived from ck/ck. cke input clock enable: cke high activates, and cke low deactivates internal clock signals, and device input buffers and output drivers. taking cke low provides precharge power-down and self refresh operation (all banks idle), or active powerdown (row active in any bank). cke is synchronous for all functions except for self refresh exit, which is achieved asynchronously. input buffers, excluding ck, ck and cke, are disabled during power-down and self refresh mode which are contrived for low standby power consumption. cs input chip select: cs enables (registere d low) and disables (registered high) the command decoder. all commands are masked when cs is registered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. ras/cas/we input command inputs: ras, cas and we (along with cs) define the command being entered. dm, ldm, udm input input data mas k: dm i s an i nput mask signal fo r w rite data. in put data i s masked whe n dm is sampled high al ong with that in put data during a write acce ss. dm is sampled on both edges of dqs. although dm pins are input-only, the dm loading matches the dq and dqs loading. ldm corresponds to the data on dq0-dq7, udm corresponds to the data on dq8-dq15. ba0,ba1 input bank address inputs: ba0 and ba1 define to which bank an active, read, write or precharge command is being applied. a [n : 0] input address inputs: provide the row address for active commands, and the column address and auto precharge bit for read / write commands, to select one location out of the memory array in the respective bank. the address inputs also provide the opcode during a mode register set command. dq0-dq15 i/o data bus: input / output ldqs,udqs i/o data strobe: output with rea d da ta, input with w rit e data. e dge-aligned with re ad da ta, centered with write data. used to capture write data. ldqs corresponds to the data on dq0-dq7, udqs corresponds to the data on dq8-dq15. nc - no connect: no internal electrical connection is presen vddq supply i/o power supply vssq supply i/o ground vdd supply power supply vss supply ground table 3 ? signal descriptions AS4C32M16MD1A-5bcn confidential - 4/56 - rev.1.2 july 2016
3.2 mobile ddr sdram addressing table item 512 mb number of banks 4 bank address pins ba0,ba1 auto precharge pin a10/ap x16 row addresses a0-a12 column addresses a0-a9 trefi(s) 7.8 table 4? addressing table AS4C32M16MD1A-5bcn confidential - 5/56 - rev.1.2 july 2016
4. block diagram 4.1 block diagram figure.2 ? block diagram AS4C32M16MD1A-5bcn confidential - 6/56 - rev.1.2 july 2016
4.2 simplified state diagram figure.3 ? state diagram AS4C32M16MD1A-5bcn confidential - 7/56 - rev.1.2 july 2016
5. function description the lpddr sdram is a high speed cmos, dynamic random-access memory internally configured as a quad-bank dram. these devices contain the following number of bits: 5 12 mb has 536,870,912 bits the lpddr sdram uses a double data rate architecture to achieve high speed operation. the double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the lpddr sdra m effectively consists of a single 2n-bit wide, one clock cycle da ta transfer at the internal dram core and two corresponding n-b it wide, one-half-clockcycle data tran sfers at the i/o pins. read and write accesses to the lpddr sdram are burst oriented; a ccesses start at a selected location and continue for a programmed number of locations in a programmed sequence. acce sses begin with the registration of an active command, which is then followed by a read or write command. the address bi ts registered coincident with the active command are used to select the bank and the row to be accessed. the address bits registered coincident with the read or write command are used to select the bank and the starting column location for the burst access. prior to normal operation, the lpddr sdram must be initialized. the following section provides detailed information covering device initialization, register definition, command description and device operation. 5.1 initialization lpddr sdrams must be powered up and initialized in a predefin ed manner. operations procedur es other than those specified may result in undefined operation. if there is any interruptio n to the device power, the initialization routine should be follo wed. the steps to be followed for device initialization are listed below. the initialization flow diagram is shown in figure 4, and the initialization flow sequence in figure 5. the mode register and extended mode register do not have default values. if they are not programmed during the initialization sequence, it may lead to unspecified operation. the clock stop feature is not available un til the device has been properly initialized from steps 1 through 11. 1. provide power, the device core power (vdd) and the device i/o power (vddq) must be brought up simultaneously to prevent device latch-up. although not required, it is recommended that vdd and vddq are from the same power source. also assert and hold clock enable (cke) to a lv-cmos logic high level 2. once the system has established consistent device power and cke is driven high, it is safe to apply stable clock 3. there must be at least 200 s of valid clocks before any command may be give n to the dram. during this time nop or deselect commands must be is sued on the command bus. 4. issue a precharge all command. 5 . p rovide nops or deselect commands for at least trp time . 6. issue an auto refresh command followed by nops or desele ct command for at least trfc time. issue the second auto refresh command followed by nops or deselect command for at least trfc time. note as part of the initialization sequence there must be two auto refresh co mmands issued. the typical flow is to issue them at step 6, but they may also be issued betwee n steps 10 and 11. 7. using the mrs command, load the base mode register. set the desired operating modes. 8 . prov ide nops or deselect commands for at least tmrd time. 9. using the mrs command, program the extended mode register for the desired operating modes. no te the order of the base and extended mode register prog ramming is not important. 10. provide nop or deselct commands for at least tmrd time. 11. the dram has been properly initialized and is ready for any valid command. AS4C32M16MD1A-5bcn confidential - 8/56 - rev.1.2 july 2016
5.1.1 initialization flow diagram figure.4 ? flow diagram AS4C32M16MD1A-5bcn confidential - 9/56 - rev.1.2 july 2016
figure 5 ? initializa tion waveform sequence AS4C32M16MD1A-5bcn confidential - 10/56 - rev.1.2 july 2016
5.2 register definition 5.2.1 mode register the mode register is used to define the specific mode of oper ation of the lpddr sdram. this definition includes the definition of a burst length, a burst type, a cas latency as shown below table. the mode register is programmed via the mode register set command (with ba0=0 and ba1=0 ) and will retain the stored information until it is reprogrammed, the device goes into deep power-down mode, or the device loses power. mode register bits a0-a2 specify the burst length, a3 the type of burst (sequential or interleave), a4-a6 the cas latency. a lo gic 0 should be programmed to all the undefined addresses bits to ensure future compatibility. the mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specif ied time t mrd before initiating any subsequent operation. violating either of these requirements will result in unspecified operation. reserved states should not be used, as unknown operation or incompatibility with future versions may result. mode ba1 ba 0 a[ n]~a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 standard mrs 0 0 reserved cas latency 010b: 2 011b: 3 burst type 0:sequential 1:interleave burst length 001b : 2 010b : 4 011b : 8 100b : 16 reserved 0 1 reserved extended mrs 1 0 reserved drive strength 000b: full strength driver 001b: half strength driver 010b:quarter strength driver 011b:octant strength driver 100b:threequarters strength driver reserved pasr 000b : all banks 001b : 1/2 array(ba1=0) 010b : ? array(ba1=ba0=0) 101b : 1/8 array (ba1 = ba0 = row addr msb = 0) 110b : 1/16 array (ba1=ba0 = row addr 2 msb = 0) table 5 ? mode register table 5.2.1.1 burst length read and write accesses to the lpddr sdram are burst oriented, with the burst length being set as in table 5, and the burst order as in table 6. the bur st length determines the ma ximum num ber of column l ocati ons that can be acces sed for a given re ad or writ e command. burst lengths of 2, 4, or 8 locatio ns are av ailable for b oth the sequential and the in terlea ved burs t ty pes. a burst leng th of 16 is optional and some vendors may cho ose to imp lement it. AS4C32M16MD1A-5bcn confidential - 11/56 - rev.1.2 july 2016
5.2.1.2 burst definition burst length starting column address order of accesses within a burst (hexadecimal notation) a3 a2 a1 a0 sequential interleaved 2 0 0 ? 1 0 ? 1 1 1 ? 0 1 ? 0 4 0 0 0 ? 1 ? 2 ? 3 0 ? 1 ? 2 ? 3 0 1 1 ? 2 ? 3 ? 0 1 ? 0 ? 3 ? 2 1 0 2 ? 3 ? 0 ? 1 2 ? 3 ? 0 ? 1 1 1 3 ? 0 ? 1 ? 2 3 ? 2 ? 1 ? 0 8 0 0 0 0 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 0 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 0 0 1 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 ? 0 1 ? 0 ? 3 ? 2 ? 5 ? 4 ? 7 ? 6 0 1 0 2 ? 3 ? 4 ? 5 ? 6 ? 7 ? 0 ? 1 2 ? 3 ? 0 ? 1 ? 6 ? 7 ? 4 ? 5 0 1 1 3 ? 4 ? 5 ? 6 ? 7 ? 0 ? 1 ? 2 3 ? 2 ? 1 ? 0 ? 7 ? 6 ? 5 ? 4 1 0 0 4 ? 5 ? 6 ? 7 ? 0 ? 1 ? 2 ? 3 4 ? 5 ? 6 ? 7 ? 0 ? 1 ? 2 ? 3 1 0 1 5 ? 6 ? 7 ? 0 ? 1 ? 2 ? 3 ? 4 5 ? 4 ? 7 ? 6 ? 1 ? 0 ? 3 ? 2 1 1 0 6 ? 7 ? 0 ? 1 ? 2 ? 3 ? 4 ? 5 6 ? 7 ? 4 ? 5 ? 2 ? 3 ? 0 ? 1 1 1 1 7 ? 0 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 7 ? 6 ? 5 ? 4 ? 3 ? 2 ? 1 ? 0 16 0 0 0 0 0-1-2-3-4-5-6-7- 8-9-a-b-c-d-e-f 0-1-2-3-4-5-6-7-8-9-a-b-c-d-e-f 0 0 0 1 1-2-3-4-5-6-7-8-9-a-b-c-d-e- f-0 1-0-3-2-5-4-7-6-9-8-b-a-d-c-f-e 0 0 1 0 2-3-4-5-6-7-8-9- a-b-c-d-e-f-0-1 2-3-0-1- 6-7-4-5-a-b- 8-9-e-f-c-d 0 0 1 1 3-4-5-6-7-8-9-a- b-c-d-e-f-0-1-2 3-2-1-0- 7-6-5-4-b-a-9-8-f-e-d-c 0 1 0 0 4-5-6-7-8-9-a-b-c-d-e-f-0-1- 2-3 4-5-6-7-0-1-2- 3-c-d-e-f-8-9-a-b 0 1 0 1 5-6-7-8-9-a-b-c- d-e-f-0-1-2-3-4 5-4-7-6- 1-0-3-2-d-c- f-e-9-8-b-a 0 1 1 0 6-7-8-9-a-b-c-d- e-f-0-1-2-3-4-5 6-7-4-5- 2-3-0-1-e-f- c-d-a-b-8-9 0 1 1 1 7-8-9-a-b-c-d-e-f-0-1-2-3-4- 5-6 7-6-5-4-3-2-1- 0-f-e-d-c-b-a-9-8 1 0 0 0 8-9-a-b-c-d-e-f- 0-1-2-3-4-5-6-7 8-9-a-b- c-d-e-f-0-1-2-3-4-5-6-7 1 0 0 1 9-a-b-c-d-e-f-0- 1-2-3-4-5-6-7-8 9-8-b-a- d-c-f-e-1-0-3-2-5-4-7-6 1 0 1 0 a-b-c-d-e-f-0-1-2-3-4-5-6-7- 8-9 a-b-8-9-e-f-c- d-2-3-0-1-6-7-4-5 1 0 1 1 b-c-d-e-f-0-1-2-3-4-5-6-7-8- 9-a b-a-9-8-f-e-d- c-3-2-1-0-7-6-5-4 1 1 0 0 c-d-e-f-0-1-2-3- 4-5-6-7-8-9-a-b c-d-e-f- 8-9-a-b-4-5-6-7-0-1-2-3 1 1 0 1 d-e-f-0-1-2-3-4- 5-6-7-8-9-a-b-c d-c-f-e- 9-8-b-a-5-4-7-6-1-0-3-2 1 1 1 0 e-f-0-1-2-3-4-5-6-7-8-9-a-b- c-d e-f-c-d-a-b-8- 9-6-7-4-5-2-3-0-1 1 1 1 1 f-0-1-2-3-4-5-6- 7-8-9-a-b-c-d-e f-e-d-c-b-a-9-8- 7-6-5-4-3-2-1-0 table 6 ? burst definition AS4C32M16MD1A-5bcn confidential - 12/56 - rev.1.2 july 2016
no t es: 1. 16-word burst length is optional. 2. for a burst length of two, a1-an selects the two data element block; a0 selects the first access within the block. 3. for a burst length of four, a2-an selects the four data element block; a0-a1 selects the first access within the block. 4. for a burst length of eight, a3-an selects the eight data element block; a0-a2 selects the first access within the block. 5. for the optional burst length of sixteen, a4-an selects the sixteen data element block; a0-a3 selects the first access withi n the block. 6. whenever a boundary of the block is reached within a gi ven sequence, the following access wraps within the block when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within the block, meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a1-an when the burst length is set to two, by a2-an when the burst length is set to 4, by a3- an when the burst length is set to 8 and a4-an when the burst length is set to 16 (where an is the most significant column address bit for a given configuration). the remaining (l east significant) address bit(s) is (are) used to select the starting location with in the block. the programmed burst length applies to both read and write bursts. 5.2.1.3 burs t type accesses within a given bu rst may b e programm ed to be ei ther sequential o r i nterleaved; this i s r eferred to as the bur st type a nd is selected vi a bit a3. the ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in table 5. 5.2.1.4 rea d latency the read latency, or cas latency, is the delay bet ween the regi stration of a read command and the availability of t he first piece of ou tput data. t he latency sh ould be set to 3 clocks. some v end ors may o ffer add itional options of 2 clocks and/or 4 clocks. if a read command is registered at a clock e dge n and the late ncy is 3 clocks, the first data element will be valid at n + 2t ck + t ac . if a read command is registered at a clock e dge n and the late ncy is 2 clocks, the first data element will be valid at n + t ck + t ac . lastly, if a read command is re gistered at a clock edge n and th e laten cy is 4 clocks, the first data element will be va lid at n + 3t ck +! t ac . 5.2.2 extended mode register the ex tended mode register controls functio ns beyon d those cont rolled by th e mode reg ister; th ese add itional func tions include output d r ive strength selection, temperat ure compensated self refresh (tcsr) and pa rtial array self refresh (pasr), as sho wn in t able 3. t he tcsr a nd pa sr functio ns are op tional and so me ven dors may choose no t to implement them. both t csr and pasr are effective is in self refresh m ode on ly. the ex tended mode register is programmed via the mode register set command (w ith ba 1=1 a nd ba0=0) and will reta in the stored info rmation until it is reprogrammed, the device is put in deep pow er-down mod e, or th e device loses pow er. the e xtended mode registe r must be load ed wh en all bank s are idle a nd no bu rsts are in progress, a nd the co ntroller must wait th e specified time t mrd before initiating any subseque nt operation. violatin g eith er of these requirements will result in unspecified operation. address bits a0-a 2 spe cify pa sr, a3-a 4 t he t csr, a5-a6 the driv e streng th. a lo gic 0 should be programmed to all the und efined addresses bits t o ensur e future compatibility. reserved states should not be used, as unknown operation or incompatibility with f uture versions may r esult. address bits a0-a2 spe cify p asr, a3-a4 the t csr, a5-a7 the d riv e strength. a logic 0 should be programmed t o all t he undefined add ress bits t o ensu re future compatibility. reserved states should not be used, as unknown operation or incom patibilit y w ith f uture ver sions may r esult. AS4C32M16MD1A-5bcn confidential - 13/56 - rev.1.2 july 2016
ba1 ba0 a[n]~a8 a7 a6 a5 a4 a3 a2 a1 a0 1 0 reserved drive strength 000b: full strength driver 001b: half strength driver 010b:quarter strength driver 011b:octant strength driver 100b:threequarters strength driver reserved pasr 000b : all banks 001b : 1/2 array(ba1=0) 010b : ? array(ba1=ba0=0) 101b : 1/8 array (ba1 = ba0 = row addr msb = 0) 110b : 1/16 array (ba1=ba0 = row addr 2 msb = 0) 5.2.2.1 partial array self refresh partial array self refresh (pasr) is an optional feature. with pasr, the self refresh may be restricted to a variable portion o f the total array. the whole array (default), 1/2 array, or 1/4 array could be selected. so me vendors may have additional options of 1/8 and 1/16 array refreshed as well. data outside the defined area will be lost. address bits a0 to a2 are used to set pasr. 5.2.2.2 temperature compensated self refresh this function can be used in the lpddr sdram to set refresh rates based on case temperature.this allows the system to control power as a function of temperature. addre ss bits a3 and a4 are used to set tcsr. some vendors may choose to have internal temperature compensat ed self refresh feature, which should automatically adjust the refresh rate based on the device temperature without any register update needed. to maintain backward compatibility, devices having internal tcsr, ignore (don?t care) the inputs to address bits a3 and a4 during emrs programming. 5.2.2.3 output drive strength the drive strength could be set to full or half or three- quarters strength via address bits a5 and a6 and a7. AS4C32M16MD1A-5bcn confidential - 14/56 - rev.1.2 july 2016
6. commands all commands (address and control signals) are registered on the positive edge of clock (crossing of ck going high and ck going low). figure 6 shows basic timing parameters for all commands. table 7, table 8 and table 9 provide a quick reference of available commands. table 10 and table 11 provide the current state / next stat e information. this is followed by a verbal description of each command. name (function) cs ras cas we ba a10/ap addr notes deselect (nop) h x x x x x x 2 no operation (nop) l h h h x x x 2 active (select bank and activate row) l l h h valid row row read (select bank and column and start read burst) l h l h valid l col read with ap (read burst with auto precharge) l h l h valid h col 3 write (select bank and column and start write burst) l h l l valid l col write with ap (write burst with auto precharge) l h l l valid h col 3 burst terminate or enter deep power down l h h l x x x 4, 5,12 precharge (deactivate row in selected bank) l l h l valid l x 6 precharge all (deactivate rows in all banks) l l h l x h x 6 auto refresh or enter self refresh l l l h x x x 7, 8, 9 mode register set l l l l valid op-code 10 table 7 ? truth table -commands notes: 1. all states and sequences no t shown are illegal or reserved. 2. deselect and nop are functionally interchangeable. 3. auto precharge is non-persistent. a10 high enables au to precharge, while a10 low disables auto precharge. 4. burst terminate applies to only read bursts with autopr echarge disabled. this command is undefined and should not be used for read with auto precharge enabled, and for write bursts. 5. this command is burst terminate if cke is high and deep power down entry if cke is low. 6. if a10 is low, bank address determines which bank is to be precharged. if a10 is high, all banks are precharged and ba0~ba1 are don?t care. 7. this command is auto refresh if cke is high and self refresh if cke is low. 8. all address inputs and i/o are ?don?t care? except for cke. internal refresh counters control bank and row addres sing. 9. all banks must be precharged before i ssuing an auto-refresh or self refresh command. 10. ba0 and ba1 value select between mrs and emrs. 11. cke is high for all commands shown except self refresh and deep power-down. function dm dq notes write enable l valid 1 write inhibit h x 1 table 8 ?truth table ? dm operations notes: 1. used to mask write data, provided co incident with the corresponding data. AS4C32M16MD1A-5bcn confidential - 15/56 - rev.1.2 july 2016
cken-1 cken current state commandn a ct ionn notes l l power down x maintain power down l l self refresh x maintain self refresh l l deep power down x maintain deep power down l h power down nop or deselect exit power down 5, 6, 9 l h self refresh nop or deselect exit self refresh 5, 7, 10 l h deep power down nop or deselect exit deep power down 5, 8 h l all banks idle nop or deselect precharge power down entry 5 h l bank(s) active nop or deselect active power down entry 5 h l all banks idle auto refresh self refresh entry h l all banks idle burst terminate enter deep power down h h see the other truth tables table 9 C truth table - cke [notes 1 - 10] notes: 1. cken is the logic state of cke at clock edge n; c ken-1 was the state of cke at the previous clock ed ge. 2. current state is the state of mobile ddr sdram immediately prior to clock edge n. 3. commandn is the command regi stered at clock edge n, and acti onn is the result of commandn. 4. all states and sequences no t shown are illegal or reserved. 5. deselect and nop are functionally interchangeable. 6. power down exit time (txp) should elapse before a command other than nop or deselect is issued. 7. self refresh exit time (txsr) should elapse before a command other than nop or deselect is issued. 8. the deep power-down exit procedure must be followed as discussed in the deep power-down section of the function al description. 9. the clock must toggle at leas t once during the txp period. 10. the clock must toggle at leas t once during the txsr time. basic timing parameters for commands figure.6 ? basic timing parameters AS4C32M16MD1A-5bcn confidential - 16/56 - rev.1.2 july 2016
current state cs ras cas we command action notes any h x x x deselect nop or continue previous operation l h h h no operation nop or co ntinue previous operation idle l l h h active select and activate row l l l h auto refresh auto refresh 10 l l l l mrs mode register set 10 row active l h l h read select column & start read burst l h l l write select column & start write burst l l h l precharge deactivate row in bank (or banks) 4 read (auto precharge disabled) l h l h read select column & start new read burst 5, 6 l h l l write select column & start write burst 5, 6, 13 l l h l precharge truncate read burst, start precharge l h h l burst terminate burst terminate 11 write (auto precharge disabled) l h l h read select column & start read burst 5, 6, 12 l h l l write select column & start new write burst 5, 6 l l h l precharge truncate wr ite burst & start precharge 12 table 10 ? current state bank n- command to bank n notes: 1. the table applies when both cken-1 and cken are high, and after txsr or txp has been met if the previous state was se lf refresh or power down. 2. deselect and nop are functionally interchangeable. 3. all states and sequences no t shown are illegal or reserved. 4. this command may or may not be bank specific. if all ban ks are being precharged, they must be in a valid state for precharging. 5. a command other than nop should not be issued to the same bank while a read or write burst with auto precharge is enabled. 6. the new read or write command could be auto prechrge enabled or au to precharge disabled. 7. current state definitions: idle: the bank has been precharged, and trp has been met. row active: a row in the bank has been activated, and trcd has been met. no data bursts/accesses and no register accesses are in prog ress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. w rite: a write burst has been initiated, with auto precha rge disabled, and has not yet terminated or been terminated . 8. the following states must not be in terrupted by a command issued to the same bank. desedect or nop commands or allowable commands to the other bank should be issued on any clock edge occurring during these states. allowable commands to the other bank are determi ned by its current state and this table, and according to next table. precharging: starts with the registrati on of a precharge command and ends when trp is met. once trp is met, the ban k will be in the idle state. row activating: starts with registration of an active command and ends when trcd is met. once trcd is met, the bank w ill be in the ?row active? state. read with ap enabled: starts with the registration of the r ead command with auto precharge enabled and ends when trp has been met. once trp has been met, the bank will be in the idle state. write with ap enabled: starts with registration of a writ e command with auto precharge enabled and ends when trp has been met. once trp is met, the bank will be in the idle state. 9. the following states must not be interrupted by any ex ecutable command; desedect or nop commands must be applied to each positive clock edge during these states. refreshing: starts with registration of an auto refres h command and ends when trfc is met. once trfc is met, the mobile ddr sdram will be in an ?all banks idle? state. accessing mode register: starts with registration of a mode register set command and ends when tmrd has been met. once tmrd is met, the mobile ddr sdram will be in an ?all banks idle? state. AS4C32M16MD1A-5bcn confidential - 17/56 - rev.1.2 july 2016
precha rging all: s t arts w i th the re gistra tion o f a precha rge all command and ends when trp is met. once trp is met, the bank will be in the idle state. 10. not bank-specific; requires that all bank s are idle and no bursts are in progress. 11. not bank-specific. burst terminate affects the most recent read burst, regardless of bank. 12. requires appropriate dm masking. 13. a write command may be applied after the completion of th e read burst; otherwise, a burst terminate must be used to end the read prior to asserting a write co mmand. current state cs ras cas we co m m a nd a cti o n not es any h x x x deselect nop or continue previous operation l h h h nop nop or continue previous operation idle x x x x any any command allowed to bank m row activating, active, or precharging l l h h active select and activate row l h l h read select column & start read burst 8 l h l l write select column & start write burst 8 l l h l precharge precharge read with auto precharge disabled l l h h active select and activate row l h l h read select column & start new read burst 8 l h l l write select column & start write burst 8,10 l l h l precharge precharge write with auto precharge disabled l l h h active select and activate row l h l h read select column & start read burst 8, 9 l h l l write select column & start new write burst 8 l l h l precharge precharge read with auto precharge l l h h active select and activate row l h l h read select column & start new read burst 5, 8 l h l l write select column & start write burst 5, 8, 10 l l h l precharge precharge write with auto precharge l l h h active select and activate row l h l h read select column & start read burst 5, 8 l h l l write select column & start new write burst 5, 8 l l h l precharge precharge table 11 ? current state bank n- command to bank m AS4C32M16MD1A-5bcn confidential - 18/56 - rev.1.2 july 2016
no t es: 1 . t he tab l e ap plies when both cken-1 and cken are high, and after txsr or txp has been met if the previous state was self refresh or power down. 2. deselect and nop are functionally interchangeable. 3. all states and sequences no t shown are illegal or reserved. 4. current state definitions: idle: the bank has been precharged, and trp has been met. row active: a row in the bank has been activated, and trcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharg e disabled, and has not yet te rminated or been terminated. write: a write burst has been initiated, with auto precha rge disabled, and has not yet terminated or been terminated. 5. read with ap enabled and write with ap enabled: the read wi th auto precharge enabled or write with auto precharge enabled states can be broken into two parts: the access peri od and the precharge period. for read with ap, the precharge period is defined as if the same burst was executed with au to precharge disabled and then followed with the earliest possible precharge command that still accesses all the data in the burst. for write with auto precharge, the precharge period begins when twr ends, with twr measured as if auto prechar ge was disabled. the access period starts with registration of the command and ends where the precharge period (or trp) begins. during the precharge period, of the read with auto precharge enabled or write with auto precharge enabled st ates, active, precharge, read, and write commands to the other bank may be applied; during the access period , only active and precharge commands to the other banks may be applied. in either case, all other related limitations appl y (e.g. contention between read data and write data must be avoide d). 6. auto refresh, self refresh, and mode register set commands may only be issued when all bank are idle. 7. a burst terminate command cannot be issued to another bank ; it applies to the bank represented by the current state only. 8. reads or writes listed in the command column include reads and writes with auto precharge enabled and reads and writes with auto precharge disabled. 9. requires appropriate dm masking. 10. a write command may be applied after the completion of data output, otherwise a burst terminate command must be issued to end the read prior to asserting a write command. AS4C32M16MD1A-5bcn confidential - 19/56 - rev.1.2 july 2016
7.operation 7.1. deselect the deselect function (/cs high) prevents new commands from being executed by the mobile ddr sdram. the mobile ddr sdram is effectively deselected. operations already in progress are not affected. 7.2. no operation the no operation (nop) command is used to instruct the se lected ddr sdram to perform a nop (/cs = low, / ras = /cas = /we = high). this prevents unwanted commands from being registered during idle or wa it states. operations already in progress are not affected. = don't care (high) ck ck cke cs ras cas we a0-an ba0,ba1 figure 7 ? nop command AS4C32M16MD1A-5bcn confidential - 20/56 - rev.1.2 july 2016
7.3 mode register the mode register and the extended mode register are loaded via the address inputs. see mode register and the extended mode register descriptions for further details. the mode register set command (see figure 8 ) can only be issued when all banks are idle and no bursts are in progress, and a subsequent executable command cannot be issued until tmrd (see figure 9 ) is met.the values of the mode register and extended mode register will be retained even when exiting deep power-down. figure 8 ? mode re gister set command figure 9 ? mode regist er set command timing 7.4. active before any read or write commands can be issued to a bank in the lpddr sdram, a row in that bank must be opened. this is accomplished by the active command (see figure 10 ): ba0 and ba1 select the bank, and the address inputs select the row to be activated. more than one bank can be active at any time. once a row is open, a read or write command could be issued to that row, subject to the t rcd specification. a subsequent active command to another row in the same bank c an only be issued after the previous row has been closed. the minimum time interval between two successive active commands on the same bank is defined by t rc . a subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. the minimum time interval betwe en two successive active command s on different banks is defined by t rrd . figure 11 shows the t rcd and t rrd definition. AS4C32M16MD1A-5bcn confidential - 21/56 - rev.1.2 july 2016
the row remains active until a precharge command (or read or write command with auto precharge) is issued to the bank. a precharge command (or read or write command with auto precharge ) must be issued before opening a different row in the same bank figure 10 ? active command figure 11 ? bank activation command cycle AS4C32M16MD1A-5bcn confidential - 22/56 - rev.1.2 july 2016
7.5. read the read command (see figure 12 ) is used to initiate a burst read access to an acti ve row, with a burst length as set in the mode register. ba0 and ba1 select the bank, and the address inputs select the starting column location. the value of a10 determines whether or not auto precharge is used. if auto precharge is se lected, the row being accessed will be precharged at the end of t he read burst; if auto precharge is not selected, the row will rema in open for subs equent accesses. the basic read timing parameters for dqs are shown in figure 13 ; they apply to all read operations. during read bursts, dqs is driven by the lpddr sdram along with the output data. the initial low state of the dqs is known as the read preamble; the low state coincident with last data-out element is known as th e read postamble. the first data-out eleme nt is edge aligned with the first rising edge of dqs and the successive data-out elements are edge aligned to successive edges of dqs . this is shown in figure 14 with a cas latency of 2 and 3. upon completion of a read burst, assuming no other read command has been initiated, the dqs will go to high-z. figure 12 ? read command AS4C32M16MD1A-5bcn confidential - 23/56 - rev.1.2 july 2016
figure 13 ? basic read timing parameters figure 14 ? read burst showing cas latency 7.5. 1 rea d to read data from a read burst may be concatenated or truncated by a subsequent read command. the first data from the new burst follows either the last element of a comple ted burst or the last desired element of a longer burst that is being truncated. the new read command should be issued x cycles after the first read co mmand, where x equals the number of desired data-out element pairs (pairs are required by the 2n prefet ch architecture). this is shown in figure 15 . AS4C32M16MD1A-5bcn confidential - 24/56 - rev.1.2 july 2016
a read comman d ca n be initiate d on any c l o ck cy cle follow i ng a previous read command. non-consecutive reads are shown in figure 16 . full-speed random read accesses within a page or pages can be performed as shown in figure 17 . 7.5.2 read burst terminate data from any read burst may be truncated with a burst terminate command, as shown in figure 18 . theburst terminate latency is equal to the read (cas) latency, i.e ., the burst terminate command should be issued x cycles after the read command where x equals the desired data-out element pairs. 7.5.3 read to write data from read burst must be completed or truncated befor e a subsequent write command can be issued. if truncation is necessary, the burst terminate command must be used, as shown in figure 19 for the case of nominal tdqss . 7.5.4 read to precharge a read burst may be followed by or truncated with a precharge command to the same bank (provided auto precharge was not activated). the precharge command should be issued x cycles a fter the read command, where x equal the number of desired data-out element pairs. this is shown in figure 20 . following the precharge command, a subsequent command to the same bank cannot be issued until trp is met. no te that part of the row precharge time is hidden during the access of the last data-o ut elements. in the case of a read being executed to completion, a pr echarge command issued at the opti mum time (as described above) provides the same operation that would result from read burst with auto precharge enabled. the disadvantage of the precharge command is that it requires t hat the command and address buses be availabl e at the appropriate time to issue the command. the advantage of the precharge command is that it can be used to truncate bursts. figure 15 ? consecutive read bursts AS4C32M16MD1A-5bcn confidential - 25/56 - rev.1.2 july 2016
cl=2 do n do n = don't care ba,col n read nop nop read nop nop ck ck command address dqs dq dqs dq 1) do n (or b) =data out from column n (or column b) 2) ba,col n (or b) =bank a,column n (or column b) 3) burst length=4; 3 subsequent elements of data out appear in the programmed order following do n (or b) 4) shown with nominal tac, tdqsck and tdqsq do b cl=3 ba,col b figure 16 ? non-consecutive read bursts figure 17 ? ra ndom read bursts AS4C32M16MD1A-5bcn confidential - 26/56 - rev.1.2 july 2016
. figure 18 ? terminating a read burst figure 19 ? read to write AS4C32M16MD1A-5bcn confidential - 27/56 - rev.1.2 july 2016
figure 20 ? read to precharge AS4C32M16MD1A-5bcn confidential - 28/56 - rev.1.2 july 2016
7.5.5 burst terminate the burst terminate command is used to truncate read bursts (w ith auto pre-charge disabled). the most recently registered read command prior to the burst terminate command will be truncated. note that the burst terminate command is not bank specific. this command should not be used to terminate write bursts. figure 21 ? burst terminate command 7.6 write the write command (see figure 22 ) is used to initiate a burst write access to an ac tive row, with a burst length as set in the mode register. ba0 and ba1 select the bank, and the add ress inputs select the star ting column location. the value of a10 determines whether or not auto precharge is us ed. if auto precharge is selected, the row being accessed will b e precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. basic write timing parameter s for dqs are shown in figure 23 ; they apply to all write operations. input data appearing on the data bus, is wr itten to the memory array subject to the dm input logic level appearing coincident w ith the data. if a given dm signal is registered low, the corresponding data will be written to the memory; if the dm signal is reg istered high, the corresponding data inputs will be ignored, and a write will not be executed to that byte / column location. figure 22 ? write command AS4C32M16MD1A-5bcn confidential - 29/56 - rev.1.2 july 2016
during write bursts, the first valid data-in element will be registered on the first rising edge of dqs following the write command, and the subsequent data elements will be registered on successive edges of dqs. the low state of dqs between the write command and the first rising edge is called the write preamble, and the low state on dqs following the last data-in element is called the write postamble. the time between the write command and the first corresponding rising edge of dqs (t dqss) is specified with a relatively wide range - from 75% to 125% of a clock cycle. figure 24 shows the two extremes of tdqss for a burst of 4. upon completion of a burst, assuming no other commands have been initiated, the dqs will remain high-z and any additional input data will be ignored. figure 23 basic write timing parameters AS4C32M16MD1A-5bcn confidential - 30/56 - rev.1.2 july 2016
figure 24 ? write burst (min. and max. tdqss) 7.6 .1 write to write data for any write burst may be concatenated with or truncated with a subsequent write command. in either case, a continuous flow of input data, can be maintained. the new write command ca n be issued on any positive edge of the clock following the previous write command. the first data-in element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. the new wr ite command should be issued x cycles after the first write command, where x equals the number of desired data-in element pairs. figure 25 shows concatenated write burst of 4. an example of non-consecutive write bursts is shown in figure 26 . full-speed random write accesses within a page or pages can be performed as shown in figure 27 . 7.6.2 write to read data for any write burst may be followed by a subsequent read command. to follow a write wi thout truncating the write burst, twtr should be met as shown in figure 28 . data for any write burst may be truncated by a subsequent read command as shown in figure 29 . note that the only data-in pairs that are registered prior to the twtr perio d are written to the internal array, and any subsequent data-in must be masked with dm. 7.6.3 write to precharge: data for any write burst may be followed by a subsequent precharge command to the same bank (provided auto precharge was not activated). to follow a write without truncati ng the write burst, twr should be met as shown in figure 30 . data for any write burst may be truncated by a subsequent precharge command as shown in figure 31 . note that only data-in pairs that are registered prior to the twr period are written to the internal array, and any subsequent data-in should be masked with dm, as shown in figure 31 . following the precharge command, a subsequent command to the same bank cannot be issued until trp is met AS4C32M16MD1A-5bcn confidential - 31/56 - rev.1.2 july 2016
figure 25 ? concatenated write bursts figure 26 ? non-consecutive write bursts AS4C32M16MD1A-5bcn confidential - 32/56 - rev.1.2 july 2016
figure 27 ? random write cycles figure 28 ? non-interrupting write to read AS4C32M16MD1A-5bcn confidential - 33/56 - rev.1.2 july 2016
figure 29 ? interrupting write to read figure 30 ? non-interrupting write to precharge AS4C32M16MD1A-5bcn confidential - 34/56 - rev.1.2 july 2016
ba,col n ba a(or all) ba,col b write pre nop ck ck command address 1) dl b = data in to column b. 2) an interrupted burst of 4, 8 or 16 is shown, 2 data elements are written. 3) t wr is referenced from the positive clock edge after the last desired data in pair. 4) a10 is low with the write co mmand (auto precharge is disabled) 5) *1=can be don't care for programmed burst length of 4 6) *2=for programmed burst length of 4, dqs becomes don't care at this point nop nop nop = don't care dqs dq dm t dqssmax t wr di b *1 *1 *1 *1 *2 7.7 precharge the p recharge command (see figure 32 ) is us ed to deactivate the ope n row in a particular bank or the open row in all banks. the ban k(s) will be ava ilable for a subs equent row acce ss a sp ecified time (trp) after the pr echarge command is issued. = don't care (high) ck ck cke cs ras cas we address ba=bank address (if a10 = l,otherwise don't care) ba ba0,ba1 a10 all banks one bank input a10 determines whether one or a l l banks are to be precha rg ed. in case where only one bank is to be precha rged, inputs ba0 , ba1 select the bank. otherwise ba0, ba1 are treated as ?don?t care?. once a ban k has been precharged, it is in th e idle state and must be activated prior to any read or write co mmand being issue d. a precharge command will be treated as a nop if there is no ope n row in that b ank, or if the previously op en row is already in the process of precharging. figure 31 interrupting write to precharge figure 32 precharge command AS4C32M16MD1A-5bcn confidential - 35/56 - rev.1.2 july 2016
7.8 auto precharge auto precharge is a feature which performs the same individual bank precharge function as descr ibed above, but without requirin g an explicit command. this is accomplished by using a10 (a10 = hi gh), to enable auto precharge in conjunction with a specific read or write command. a prechar ge of the bank / row that is addressed with the read or write command is automatically performed upon completion of the read or write burst. auto prechar ge is non persistent in that it is either enabled or disabled for each individual read or write command. auto precharge ensures that a precharge is initiated at the earlie st valid stage within a burst. the user must not issue anothe r command to the same bank until the precharging time (t rp ) is completed. this is determin ed as if an xplicit precharge command was issued at the earlies t possible time, as described for each burst type in the operation section of this specificati on. 7.9 refresh requirements lpddr sdram devices require a refresh of all rows in any rolling 64ms interval. each refresh is generated in one of two ways: b y an explicit auto refresh command, or by an internally tim ed event in self refresh mode. di viding the number of device rows into the rolling 64ms interval defines the average refresh interval (t refi ), which is a guideline to controllers for distributed refresh timing. 7.10 auto refresh auto refresh command (see figure 33 ) is used during normal operation of the lpddr sdram. this command is non persistent, so it must be issued each time a refresh is required. = don't care (high) ck ck cke cs ras cas we a0-an ba0,ba1 figure 33 ? auto refresh command 7.1 1 self referesh the self refresh command (see figure 34 ) can be used to retain data in the lpddr sdram, even if the rest of the system is powered down. when in the self refresh mode, the lpddr sdram retains data without external clocking. the lpddr sdram device has a built-in timer to accommodate self refresh ope ration. the self refresh command is initiated like an auto refresh command except cke is low. input signals except cke are ?don?t care? during self refresh. the user may halt the external clock one clock after the self refresh command is registered. once the command is registered, cke must be held low to keep the de vice in self refresh mode. the clock is internally disabled during self refresh operation to save power. the minimum time that the device must remain in self refresh mode is t rfc . the procedure for exiting self refresh requires a sequence of co mmands. first, the clock must be stable prior to cke going back high. once self refresh exit is registered, a delay of at least t xs must be satisfied before a valid command can be issued to the device to allow for completion of any internal refresh in progress. the use of self refresh mode introduces the possibility that an internally timed refresh event can be missed when cke is raised for exit from self refresh mode. upon exit from self refresh an extra auto refresh command is recommended. figure 36 shows self refresh entry and exit. in the self refresh mode, two additional power-saving options ex ist: temperature compensated self refresh (tcsr) and partial array self refresh (pasr); they are describ ed in the extended mode register section . AS4C32M16MD1A-5bcn confidential - 36/56 - rev.1.2 july 2016
figure 34 ? self refresh command figure 35 ? auto refresh cycles back-to-back AS4C32M16MD1A-5bcn confidential - 37/56 - rev.1.2 july 2016
figure 36 ? self refresh entry and exit 7. 12 power down power-down is entered when cke is registered low (no accesses c an be in progress). if power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if powe r-down occurs when there is a row active in any bank, this mode is referred to as active power-down. entering power-down deactivates the input and output buffers, ex cluding ck, ck and cke. in pow er-down mode, cke low must be maintained, and all other input signals are ?don?t care ?. the minimum power-down duration is specified by t cke . however, power- down duration is limited by the refresh requirements of the device. the power-down state is synchronously exited when cke is registered high (along with a nop or deselect command). a valid command may be applied t xp after exit from power-down. figure 37 shows power-down entry and exit. for clock stop during power-down mode, please refer to the clock stop subsection in this specification AS4C32M16MD1A-5bcn confidential - 38/56 - rev.1.2 july 2016
figure 37 ? power-down entry and exit AS4C32M16MD1A-5bcn confidential - 39/56 - rev.1.2 july 2016
7.13 deep power down the deep power-down (dpd) mode enables very low standby curr ents. all internal voltage generators inside the lpddr sdram are stopped and all memory data is lost in this mode. all the info rmation in the mode register and the extended mode register i s lost. deep power-down is entered using the burst terminate command (see figure 21 ) except that cke is registered low. all banks must be in idle state with no activity on the data bus prio r to entering the dpd mode. while in this state, cke must be h eld in a constant low state. to exit the dpd mode, cke is taken high after the clock is stable and nop commands must be maintained for at least 200 s. after 200 s a complete re-initialization is required following step s 4 through 11 as defined for the initialization sequence. deep power-down entry and exit is shown in figure 38 . figure 38 ? deep power-down entry and exit AS4C32M16MD1A-5bcn confidential - 40/56 - rev.1.2 july 2016
7.14 clock stop stopping a clock during idle periods is an effe ctive method of reducing power consumption. the lpddr sdram supports clock stop under the following conditions: ? the last command (active, read, write, precharge, au to refresh or mode register set) has executed to completion, including any data-out during r ead bursts; the number of clock pulses per access command depends on the device?s ac timing parameters and the clock frequency; ? the related timing conditions (t rcd , t wr , t rp , t rfc , t mrd ) has been met; ? cke is held high when all conditions have been met, the device is either in ?idle state? or ?row active state? and clock stop m ode may be entered with ck held low and ck held high. clock stop mode is exited by restarting the clock. at least one nop command has to be issued before the next access command may be applied. additional clock pulses might be required depending on the sy stem characteristics. figure 39 shows clock stop mode entry and exit. ? initially the device is in clock stop mode ? the clock is restarted with the rising e dge of t0 and a nop on the command inputs ? with t1 a valid access command is latched; this command is foll owed by nop commands in order to allow for clock stop as soon as this access command is completed ? tn is the last clock pulse required by the access command latched with t1 ? the clock can be stopped after tn figure 39 ? clock stop mode entry and exit AS4C32M16MD1A-5bcn confidential - 41/56 - rev.1.2 july 2016
8. electrical characteristic 8.1 absolute maximum ratings parameter symbol values units min max voltage on vdd relative to vss vdd ? 0.3 2.7 v voltage on vddq relative to vss vddq ? 0.3 2.7 v voltage on any pin relative to vss vin, vout ? 0.3 2.7 v operating temperature : tj -30 +85 c storage temperature tstg ? 55 +150 c short circuit output current iout 50 ma power dissipation pd 1.0 w 8.2 input/output capacitance [notes 1-3] parameter symbol min max units notes input capacitance, ck, ck cck 1.5 3.0 pf input capacitance delta, ck, ck cdck 0.25 pf input capacitance, all other input-only pins ci 1.5 3.0 pf input capacitance delta, all other input-only pins cdi 0.5 pf 7input/ output capacitance, dq ,dm,dqs cio 3.0 5.0 pf 4 input/output capacitance delta, dq, dm, dqs cdio 0.50 pf 4 notes: 1. these values are guaranteed by design and are tested on a sample base only. 2. these capacitance values are for single monolithic devices onl y. multiple die packages will have parallel capacitive loads. 3. although dm is an input-only pin, the input capacitance of this pin must model the input capacitance of the dq and dqs pins. this is required to match signal propagation times of dq, dqs and dm in the system. AS4C32M16MD1A-5bcn confidential - 42/56 - rev.1.2 july 2016
8.3 electrical characteristics and ac/dc operating conditions all values are recommended operating conditions unless otherwise noted. 8.3.1 electrical char acteristics and ac/dc operating conditions (vdd/vddq: 1.7~1.95v) parameter/condition symbol min max units notes supply voltage vdd 1.70 1.95 v i/o supply voltage vddq 1.70 1.95 v address and command inputs (a0~an, ba0,ba1,cke, cs , ras , cas , we ) input high voltage vih 0. 8*vddq vddq + 0.3 v input low voltage vil ? 0.3 0.2*vddq v clock inputs (ck, ck ) dc input voltage vin ? 0.3 vddq + 0.3 v dc input differential voltage vid (dc) 0.4*vddq vddq + 0.6 v 2 ac input differential voltage vid (ac) 0.6*vddq vddq + 0.6 v 2 ac differential crossing voltag e vix 0.4*vddq 0.6*vddq v 3 data inputs (dq, dm, dqs) dc input high voltage vihd (dc) 0.7*vddq vddq + 0.3 v dc input low voltage vild (dc) ? 0.3 0.3*vddq v ac input high voltage vihd (ac) 0.8*vddq vddq + 0.3 v ac input low voltage vild (ac) ? 0.3 0.2*vddq v data outputs (dq, dqs) dc output high voltage (ioh= ? 0.1ma) voh 0.9*vddq - v dc output low voltage (iol=0 .1ma) vol - 0.1*vddq v leakage current input leakage current5 lil -1 1 ua output leakage current lol -5 5 ua notes: 1. all voltages referenced to vss an d vss q must be same potential. 2 . vi d (dc) and vid (ac) are t he magnitude of the difference between the input level on ck and ck . 3. the value of vix is expected to be 0.5*vddq and must track variations in the dc level of the same. AS4C32M16MD1A-5bcn confidential - 43/56 - rev.1.2 july 2016
8.4 idd specification paramete rs and test conditions 8.4.1 idd specification parameters and test conditions,-30c ~ 85c [recommended operating conditions; notes 1-3] (512mb, x16) parameter symbol test condition -5 unit operating one bank active- precharge current idd0 trc = trcmin ; tck = tckmin ; cke is high; cs is high between valid commands; address inputs are switching; data bus inputs are stable 40 ma precharge power-down standby current idd2p all banks idle, cke is low; cs is high, tck = tckmin ; address and control inputs are switching; data bus inputs are stable 0.3 ma precharge power-down standby current with clock stop idd2ps all banks idle, cke is low; cs is high, ck = low, ck = high; address and control inputs are switching; data bus inputs are stable 0.3 ma precharge non power-down standby current idd2n all banks idle, cke is high; cs is high, tck = tckmin; address and control inputs are switching; data bus inputs are stable 10 ma precharge non power-down standby current with clock stop idd2ns all banks idle, cke is high; cs is high, ck = low, ck = high; address and control inputs are switching; data bus inputs are stable 3 ma active power- down standby current idd3p one bank active, cke is low; cs is high, tck = tckmin;address and control inputs are switching; data bus inputs are stable 3 ma active power- down standby current with clock stop idd3ps one bank active, cke is low; cs is high, ck = low, ck = high; address and control inputs are switching; data bus inputs are stable 3 ma active non power-down standby current idd3n one bank active, cke is high; cs is high, tck = tckmin; address and control inputs are switching; data bus inputs are stable 25 ma active non power-down standby current with clock stop idd3ns one bank active, cke is high; cs is high, ck = low, ck = high; address and control inputs are switching; data bus inputs are stable 15 ma operating burst read current idd4r one bank active; bl = 4; cl = 3; tck = tckmin ; continuous read bursts; iout = 0 ma; address inputs are switching; 50% data change each burst transfer 85 ma operating burst write current idd4w one bank active; bl = 4; tck = tckmin ; continuous write bursts; address inputs are switching; 50% data change each burst transfer 65 ma auto-refresh current idd5 trc = trfcmin ; tck = tckmin ; burst refresh; cke is high; address and control inputs are switching; data bus inputs are stable 75 ma deep power- down current idd8(4) address and control inputs are stable; data bus inputs are stable 10 ua AS4C32M16MD1A-5bcn confidential - 44/56 - rev.1.2 july 2016
notes: 1. idd specifications are tested after the device is properly initialized. 2. input slew rate is 1v/ns. 3. definitions for idd: lo w is defined as v in 0.1 * v ddq ; high is defined as v in 0.9 * v ddq ; stable is defined as inputs stable at a high or low level; switching is defined as: - address and command: inputs changing between high and low once per two clock cycles; - data bus inputs: dq changing between high and low once per clock cycle; dm and dqs are stable. 4. idd8 is a typical v alue at 30. idd6 conditions : i dd6 units tcsr range 45 85 ua full array 350 500 1/2 array 280 450 1/4 array 250 400 notes: 1. measured with outputs open. 2. internal tcsr can be supported. AS4C32M16MD1A-5bcn confidential - 45/56 - rev.1.2 july 2016
8.5 ac timings 8.5.1 ac timing table [recommended operating conditions: notes 1-29] parameter symbol - 5 unit notes min max dq output access time from ck/ ck cl=3 tac 2.0 5.0 ns cl=2 2.0 6.5 dqs output access time from ck/ ck cl=3 tdqsck 2.0 5.0 ns cl=2 2.0 6.5 clock high-level width tch 0.45 0.55 tck clock low-level width tcl 0.45 0.55 tck clock half period thp min (tcl, tch) ns 10,11 clock cycle time cl=3 tck 5 ns 12 cl=2 12 ns 12 dq and dm input setup time fast slew rate tds 0.48 ns 13,14,15 slow slew rate 0.58 ns 13,14,16 dq and dm input hold time fast slew rate tdh 0.48 ns 13,14,15 slow slew rate 0.58 ns 13,14,16 dq and dm input pulse width tdipw 1.4 ns 17 address and control input setup time fast slew rate tis 0.9 ns 15,18 slow slew rate 1.1 ns 16,18 address and control input hold time fast slew rate tih 0.9 ns 15,18 slow slew rate 1.1 ns 16,18 address and control input pulse width tipw 2.3 ns 17 dq & dqs low-impedance time from ck/ ck tlz 1.0 ns 19 dq & dqs high-impedance time from ck/ ck cl=3 thz 5.0 ns 19 cl=2 6.5 dqs-dq skew tdqsq 0.4 ns 20 dq/dqs output hold time from dqs tqh thp-tqhs ns 11 data hold skew factor tqhs 0.5 ns 11 write command to 1st dqs latching transition tdqss 0.75 1.25 tck dqs input high-level width tdqsh 0.4 0.6 tck dqs input low-level width tdqsl 0.4 0.6 tck dqs falling edge to ck setup time tdss 0.2 tck dqs falling edge hold time from ck tdsh 0.2 tck mode register set command period tmrd 2 tck write preamble setup time twpres 0 ns 21 write postamble twpst 0.4 0.6 tck 22 write preamble twpre 0.25 tck read preamble cl = 3 trpre 0.9 1.1 tck 23 cl = 2 0.5 1.1 tck 23 read postamble trpst 0.4 0.6 tck active to precharge command period tras 40 70,000 ns active to active command period trc tras+ trp ns auto refresh to active/auto refresh command period trfc 72 ns AS4C32M16MD1A-5bcn confidential - 46/56 - rev.1.2 july 2016
pa ra m et er sym bol - 5 uni t no tes min max active to read or write delay trcd 15 ns precharge command period trp 3 tck active bank a to active bank b delay trrd 10 ns write recovery time twr 15 ns 24 auto precharge write recovery + precharge time tdal - tck 25 internal write to read command delay twtr 1 tck self refresh exit to next valid command delay txsr 120 ns 26 exit power down to next valid command delay txp 2 tck 27 cke min. pulse width (high and low pulse width) tcke 1 tck refresh period tref 64 ms average periodic refresh interval (x16) trefi 7.8 s 28,29 notes: 1. all voltages referenced to vss. 2. all parameters assume proper device initialization. 3. tests for ac timing may be conducted at nominal supply volta ge levels, but the related specifications and device operation are guaranteed for the full voltage and temperature range sp ecified. 4. the circuit shown below represents the timing reference load us ed in defining the relevant timing parameters of the part. it is not intended to be either a precise representation of the ty pical system environment nor a depiction of the actual load presented by a production tester. system designers will use ibis or other simulation tools to correlate the timing referenc e load to system environment. manufacturers will correlate to their production test conditions (ge nerally a coaxial transmission lin e terminated at the tester electronics) . for the half strength driver with a nomi nal 10pf load parameters tac and tqh are expected to be in the same range. however, these parameters ar e not subject to production test but are estimated by design / characterization. use of ibis or other simulation tools for system design validation is suggested. 5. t he ck/ ck input reference voltage level (f or timing referenced to ck/ ck ) is the point at which ck and ck cross; the input reference voltage level for signals other than ck/ ck is vddq/2. 6. the timing reference voltage level is vddq/2. 7. ac and dc input and output voltage levels are defined in the section for electrical c haracteristics and ac/dc operating conditions. 8. a ck/ ck differential slew rate of 2.0 v/ ns is assumed for all parameters. 9. cas latency definition: with cl = 3 the first data element is valid at (2 * tck + tac) after the clock at which the read command was registered; with cl = 2 the first data element is valid at (tck + tac) after the clock at which the read command was registered 10. min (tcl, tch) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits of tcl and tch) 11. tqh = thp - tqhs, where thp = minimum half clock period for any given cycle and is defined by clock high or clock low (tcl, tch). tqhs accounts for 1) the pulse durat ion distortion of on-chip clock circuits; and 2) the worst case push-out of dqs on AS4C32M16MD1A-5bcn confidential - 47/56 - rev.1.2 july 2016
o ne tra n sition follow e d by the worst case pull-in of dq on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. 12. the only time that the clock frequency is allowed to chan ge is during clock stop, power-down or self-refresh modes. 13. the transition time for dq, dm and dqs inputs is measured between vil(dc) to vih(ac) for rising input signals, and vi h(dc) to vil(ac) for falling input sig nals. 14. dqs, dm and dq input slew rate is specified to prevent d ouble clocking of data and preserve setup and hold times. signal transitions through the dc region must be monotonic. 15. input slew rate 1.0 v/ns. 16. input slew rate 0.5 v/ns and < 1.0 v/ns. 17. these parameters guarantee device timing but they are not necessarily tested on each device. 18. the transition time for address and comm and inputs is measured between vih and vil. 19. thz and tlz transitions occur in the same access time window s as valid data transitions. these parameters are not referred to a specific voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 20. tdqsq consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle. 21. the specific requirement is that dqs be valid (high, lo w, or some point on a valid transition) on or before the corresponding ck edge. a valid transition is defined as monot onic and meeting the input slew rate specifications of the device. when no writes were previously in progress on the bus, dqs will be transitioning from hi-z to logic low. if a p revious write was in progress, dqs coul d be high, low, or transitioning from hi gh to low at this time, depending on tdqss. 22 . the maximum limit for this parameter is not a device limit. the device operates with a greater value for this parameter, bu t system performance (bus turnaround) will degrade accordingly. 23 . a low level on dqs may be maintained during high-z states (dqs drivers disabled) by addi ng a weak pull-down element in the system. it is recommended to turn off the weak pull-down el ement during read and write bursts (dqs drivers enabled). 24. at least one clock cycle is required during twr time when in auto precharge mode. 25. minimum 3 clocks of tdal (=twr + trp) is required be cause it need minimum 2 clocks for twr and minimum 1 clock for trp. tdal = (twr/tck) + (trp/tck): for each of the terms above, if not already an integer, round to the next higher integer. 26. there must be at least two cl ock pulses during the txsr period. 27. there must be at least one clock pulse during the txp period. 28. trefi values are dependence on density and bus wi dth. 29. a maximum of 8 refresh commands can be posted to any gi ven m, meaning that the maximum absolute interval between any refresh command and the next refresh command is 8*trefi. cas latency definition (with cl=3) AS4C32M16MD1A-5bcn confidential - 48/56 - rev.1.2 july 2016
AS4C32M16MD1A-5bcn confidential - 49/56 - rev.1.2 july 2016
8.5.2 output slew rate characteristics parameter min max unit notes pull-up and pull-down slew rate for full strength driver 0.7 2.5 v/ns 1,2 pull-up and pull-down slew rate for three- quarter strength driver 0.5 1.75 v/ns 1,2 pull-up and pull-down slew rate for half strength driver 0.3 1.0 v/ns 1,2 output slew rate matching ratio (pull-up to pull-down) 0.7 1.4 - 3 notes: 1. measured with a test load of 20 pf connected to v ssq . 2. output slew rate for rising edge is measured between vild(dc) to vihd(ac) and for falling edge between vihd(dc) to vild(ac). 3. the ratio of pull-up slew rate to pull-down slew rate is specified for the same temperature and voltage, over the entire tem perature and voltage range. for a given output, it represents the maximum difference between pull-up and pull-down drivers due to process va riation. 8.5.3 ac overshoot/u ndershoot specification parameter specification maximum peak amplitude allowed for overshoot 0.5 v maximum peak amplitude allowed for undershoot 0.5 v the area between overshoot signal and vdd must be less than or equal to 3 v-ns the area between undershoot signal and gnd must be less than or equal to 3 v-ns AS4C32M16MD1A-5bcn confidential - 50/56 - rev.1.2 july 2016
8.5.4 ac overshoot and undershoot definition figure 40 ? ac oversh oot a nd undersh oot definition AS4C32M16MD1A-5bcn confidential - 51/56 - rev.1.2 july 2016
9. package dimension 60ball fine pitch bga (8.0x9.0mm) AS4C32M16MD1A-5bcn confidential - 52/56 - rev.1.2 july 2016
alliance memory, inc. 511 taylor way, san carlos, ca 94070 tel: 650-610-6800 fax: 650-620-9211 www.alliancememory.com copyright ? alliance memory all rights reserved ? copyright 2007 alliance memory, inc. all rights reserved. our three-point logo, our name and intelliwatt are trademarks or registered trademarks of alliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to this document and its products at any time without notice. alliance assumes no responsibility for any errors that may appear in this document. the data contained herein represents alliance's best data and/or estimates at the time of issuance. alliance reserves the right to change or correct this data at any time, without notice. if the product described herein is under development, significant changes to these specifications are possible. the information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in alliance's terms and conditions of sale (which are available from alliance). all sales of alliance products are made exclusively according to alliance's terms and conditions of sale. the purchase of products from alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of alliance or third parties. alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify alliance against all claims arising from such use. part numbering system as4c 32m16md1a 5 b c n dram 32m16=32mx1 6 md1=mobile ddr 1 a=a die 5= 200mhz b = f pbga (fine pitch ball grid array) indicates pb and halogen free c=extended (-30c+85c) AS4C32M16MD1A-5bcn confidential - 5 3/53 - rev.1.2 july 2016

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